1. Field of the Invention
The present invention relates to a technology for testing semiconductor devices and, more particularly, to a technology of controlling the period (test rate) of a test pattern.
2. Description of the Related Art
A test apparatus is used to supply a test pattern to a device under test (DUT) so as to determine whether the device is defective or not by inspecting its operation. A pattern generator (PG) for generating a test pattern to be supplied to a DUT and a timing generator (TG) for defining the timing of supplying a test pattern to a DUT are installed in a test apparatus. The period (frequency) of a test pattern is alternatively referred to as a test rate. A test apparatus is required to provide the function of altering a test rate arbitrarily.
Timing generators are broadly categorized into two types according to the method of operation.
The first method uses a phase lock loop (PLL). Specifically, a PLL circuit is used to multiply a reference clock and the timing of a test pattern is controlled in synchronization with the multiplied signal. The PLL method allows setting a test rate arbitrarily by switching the frequency division ratio of the PLL circuit. Hereinafter, this method will also be referred to as the PLL method.
The second method uses a variable delay circuit. This method achieves an arbitrary test rate by setting the amount of delay of a variable delay circuit according to a test rate and delay the test pattern accordingly. Alternatively a variable delay circuit introduces an arbitrary delay in a set signal and a reset signal defining the timing of transition of a test pattern so that a test pattern is caused to make a transition in synchronization with the set signal and the reset signal thus delayed. This method will also be referred to as a phase accumulation (PA) method.
Semiconductor devices available today operate at increasingly higher speeds. Higher speeds of devices mean higher test rates. In the near future, a test apparatus will be required to control a test rate with an extremely high resolution on the order of sub-picoseconds (ps).
For high resolution control of a test rate in a PLL-based timing generator, either (1) the pulse swallow method or (2) ΔΣ fractional N-PLL method is employed. The pulse swallow method has an advantage in that the design is easy but has a disadvantage in that there are some frequency division ratios that cannot be set (i.e., test rates that cannot be set). Meanwhile, the ΔΣ fractional N-PLL method has an advantage in that arbitrary frequency division ratios (test rates) can be achieved but has a disadvantage in that fractional spurious is generated. Providing a ΔΣ noise shaper to eliminate fractional spurious will cause another problem in that phase noise is increased. Still another problem is that spurious signals will be increased at a specific frequency division ratio.
A test apparatus targeting memory devices and some non-memory devices is sometimes required to change the test rate from moment to moment on a real time basis. Such a control is sometimes referred to as real time timing control (RTTC) or on the fly control. In principle, on the fly control using a PLL-based timing generator is impossible because of a settling time (lock up time) required to elapse until the PLL produces oscillation at a preset period.
Meanwhile, switching of the test rate in a PA-based timing generator is none other than switching of the amount of delay of the variable delay circuit. Since the switching of the amount of delay of the variable delay circuit only requires a very short time, the PA method is employed for on the fly control of the test rate.
The resolution of the test rate of the PA-based timing generator corresponds to the resolution of the amount of delay of the variable delay circuit. Variable delay circuits currently available provide a resolution of one to several ps. To obtain a higher resolution (e.g., sub ps), a dramatic increase in hardware scale would be required or it would be almost impossible to design such a circuit.